The invention relates to an information processing system including a memory device and a memory control apparatus having a plurality of cache memories and, more particularly, to a memory control apparatus of an information processing system in which a memory device uses a Redundant Array of Inexpensive Disks (RAID) technique.
In a conventional memory control apparatus having a cache memory, in response to a write instruction from a central processing unit, completion of a writing process is reported to the central processing unit when write data has been stored into the cache memory in the memory control apparatus. The storage of the write data into a disk device is executed by the memory control apparatus asynchronously with the write instruction from the central processing unit. Such a control is called a write-after control. In the write-after control, when the end of writing process is reported to the central processing unit, since data is not transferred to the disk device, a high-speed response to the central processing unit can be performed.
In the data stored in the cache memory, the data before it is transferred to the disk device is called dirty data, and the data which coincides with the data in the disk device is called clean data. In an information processing apparatus for performing the write-after control, dirty data is data which exists only on the cache memory in the memory control apparatus. Therefore, the dirty data cannot be deleted until the transfer to the disk device is finished.
Data transfer speed between the cache memory and the disk device is slower than data transfer speed between the central processing unit and the cache memory. There is consequently, a case where the cache memory is filled with the dirty data at the time of the write-after control. Therefore, a memory control apparatus disclosed in JP-A-4-264940 monitors an amount of dirty data in the cache, an inflow amount of write data to the cache memory of each memory device, and an outflow amount of dirty data due to the write-after process. When the dirty data amount in the cache reaches a certain threshold value (permission amount), a limitation of the allocation of the cache memory to the write data and a data writing preferential execution to the memory device are executed for the memory device in which (the inflow amount) greater than (the outflow amount). Due to the above control, a deterioration in performance of the whole system caused by the cache memory entering a full state is avoided and the distribution of the allocation of the cache memory for every memory device can be properly performed.
In the write-after process, since the cache memory is volatile, there is a possibility that the dirty data is deleted due to a fault of a power source of a control apparatus or the like, a fault of a hardware of the cache memory, or the like. Therefore, in xe2x80x9cEvolution of the DASD storage controlxe2x80x9d disclosed in IBM SYSTEMS JOURNAL, Vol. 28, No. 2, 1989, a memory control apparatus has therein a cache memory and a non-volatile storage (NVS) of a small capacity for backup of dirty data, and the dirty data is duplexed and held in the cache memory and non-volatile storage (NVS), thereby preventing deletion of the dirty data.
Further, a memory control apparatus having a plurality of cache memories which is backed up by a battery is disclosed in JP-A-5-189314. The memory control apparatus has a cache memory whose power source is depleted by a battery backup. The cache memory is divided into N portions and data read out from a memory device by a command from an upper apparatus is stored into an arbitrary one of the N divided portions of the cache memory. Data which is written into the cache memory by an instruction from the upper apparatus is stored into two arbitrary ones of the N divided portions of the cache memory. Thus, performance of the data at the time of a fault is improved and a deterioration of the performance can be prevented.
When using the RAID technique for the disk device as a memory device, the memory control apparatus needs to form parity data to guarantee data at the time of the write-after process. Therefore, both the dirty data (write data) and the clean data (data which is updated by the write data) need to be held on the cache memory.
In the memory control apparatus disclosed in JP-A-5-189314 in which data is duplexed and stored into a plurality of cache memories, the amount of data which cannot be deleted until the data transfer to the disk device is completed is largely divided between the depleted cache memories depending on an allocating method of the cache memory for the clean data. When an amount of dirty data (including the clean data to form parity data) in one cache memory reaches a cache memory capacity or a preset dirty data threshold value (permission amount), even in the case where there is a usable area in the other cache memory, the dirty data cannot be duplexed Thus, a response by the write-after process cannot be performed and the performance deteriorates.
FIGS. 8(a) and 8(b) show a case where a cache surface (cache for storing clean data and dirty data as updated data of the clean data) and an NVS surface (cache to store the dirty data) of each of a cache A 80 and a cache B 81 of a memory control apparatus are fixedly used.
When using one of the two cache memories as a cache surface and the other as an NVS surface, as shown in FIG. 8(a), an amount of dirty data in the cache A 80 that is used as a cache surface is larger than an amount of dirty data in the cache B 81 that is used as an NVS surface. Thus, as shown in FIG. 8(b), when the cache A 80 which is used as a cache surface is filled with the dirty data, in spite of the fact that a new usable area c still remains in the cache B 81, the dirty data cannot be duplexed. Therefore, the write-after process cannot be performed.
An object of the invention relates to an allocation of cache memories and intends to improve the efficiency using or allocating of cache memory space by controlling a balance of using states of a plurality of cache memories.
A To accomplish the above object, a memory control apparatus according to the invention comprises: a channel control unit, interposed between a central processing unit and a memory device for storing data, for controlling a data transfer to/from the central processing unit; a drive control unit for controlling data transfer to/from the memory device; a plurality of cache memories for temporarily storing data that is transferred between the central processing unit and the memory device; and a cache memory control unit having selecting means for selecting the cache memory to store data which is transferred from the memory device. The selecting device arbitrarily selects a first cache memory which is used as a cache surface and a second cache memory which is used as an NVS surface from among a plurality of cache memories. There is a case where the cache memory control unit of the memory control apparatus has a memory device for storing control information of the memory control apparatus.
When the data is read out from the memory device, the memory control apparatus transfers the read data to the central processing unit and stores the data in the cache memory. In this instance, a memory control apparatus arbitrarily selects the cache memory, which is used as a cache surface (a cache for storing clean data and dirty data which is updated data of the clean data) from a plurality of cache memories, and stores the data in the selected cache memory.
When the data is written into the memory device, on the other hand, the memory control apparatus stores the write data transferred from the central processing unit into the cache memory. In this instance, when the data which is updated by the write data has been stored as clean data in the cache memory, the cache memory is used as a cache surface, and clean data and dirty data which is updated data of the clean data are stored in the cache surface. The memory control apparatus arbitrarily selects the cache memory which is used as a non-volatile storage (NVS) surface from a plurality of cache memories and stores the dirty data into the cache memory.
As a specific method for when the memory control apparatus selects the cache memory, there is a method of selecting a cache memory on the basis of a virtual or physical address or an identifier of data such as a sequence number or the like when dividing into management units.
There is another method including the steps of: storing usable/unusable state information of each of the unit memories included in the cache memory into the control memory of the memory control apparatus; and calculating the number of usable unit memories of each of the cache memories with reference to the usable/unusable state information of each of the unit memories, and wherein the cache memory is selected by the usable unit memory.
There is yet another method including the steps of: storing memory usage amount information for each of the cache memories into the control memory of the memory control apparatus; arbitrarily selecting the first cache memory and the second cache memory from a plurality of cache memories on the basis of the memory usage amount information of each of the cache memories; and storing dirty data amount information for each of the cache memories or clean data amount information to form parity data in the control memory, and wherein the cache memory is selected on the basis of the dirty data amount information of each of the cache memories or the clean data amount information to form the parity data.
According to the invention, when data is read out from the memory device, the memory control apparatus selects the cache memory which is used as a cache surface from a plurality of cache memories and stores the read data as clean data into the selected cache memory. When updating the clean data, the memory control apparatus selects the cache memory which is used as an NVS surface from the plurality of cache memories and stores the write data into each of the cache memories which are used as a cache surface and an NVS surface. In this instance the clean data stored in the cache memory that is used as a cache surface is also held in the cache memory.
As mentioned above, the memory control apparatus according to the invention arbitrarily selects the cache memories to be used as a cache surface and an NVS surface from the plurality of cache memories. Therefore, a deviation of the using states among the plurality of cache memories can be reduced.
When the memory control apparatus selects the cache memory on the basis of an address of the data or a sequence number of the data, the data of a certain group unit having certain characteristics is divided and allocated into the plurality of cache memories by the address or sequence number of the data. Therefore, expected values of probabilities at which the data in the cache memory is updated are averaged among the plurality of cache memories and a cache memory space can be effectively used. That is, the probability of the data to be updated differs depending on the characteristics of the data. Therefore, by allocating a group of data to the same cache memory, the occurrence of a deviation of the dirty data amounts among the plurality of cache memories in accordance with the data characteristics is prevented, so that which cache memory is allocated to the divided data is decided by an identifier of the data.
When the memory control apparatus selects the cache memory on the basis of the number of requests for the allocation of the cache memory, the memory control apparatus has means for storing the number of processes by the cache memory selecting process or the number of blocks allocated to the control memory. The memory control apparatus selects the cache memory on the basis of the number of processing times or the number of blocks. Therefore, since the probability values at which the data in the cache memory is updated are averaged among the plurality of cache memories, the cache memory space can be effectively used.
Further, when the memory control apparatus selects the cache memory on the basis of the cache memory using state, the memory control apparatus has means for storing the using state information of each of the plurality of cache memories in the control memory. The memory control apparatus selects which cache memory is allocated in accordance with the using state of the cache memory. According to the above control method, by averaging the present using states of the cache memories, the cache memory space is effectively used.
On the other hand, the cache memory in the memory control apparatus of the invention includes a plurality of unit memories and can close every unit memory. When a certain unit memory is closed, the cache memory including the closed unit memory is called a degenerate state. When there is a cache memory in the degenerate state, a balance of the capacities among the plurality of cache memories is divided. Therefore, it is necessary to control the memory allocation in consideration of a capacity ratio of the cache memory. For this purpose, the memory control apparatus has means for storing the closed state information of each unit memory as a component element of the plurality of cache memories, calculating the capacity of each cache memory by the closed state information, and selecting the cache memory to be allocated in accordance with a capacity ratio. In this instance, the above method can be also commonly used.